1. Field of the Invention
The present invention relates to a synchronizing circuit, and more particularly to a synchronizing circuit that can carry out reduced power consumption at a time of a power supply interruption.
2. Description of the Related Art
In recent years, increases in the scale and functionality of LSIs are proceeding accompanying the development of semiconductors. On the other hand, reductions in standby power are being sought for portable devices and sensor networks and the like. In a high function LSI, all of the functions are not in constant operation, and reduced power consumption can be realized by stopping the operations of circuit sections that are not operating. Although a gated clock method may be mentioned as a well known method, in recent years attention is being focused on internal partial power supply interruption technology that is more effective than the gated clock method.
The term “internal partial power supply interruption technology” refers to technology that stops a power supply of only one portion inside an LSI by inserting a switch or a regulator into a power line or a ground line of the LSI.
For example, a semiconductor integrated circuit device has been proposed that controls the supply or interruption of power with respect to a function block that is an internal partial power supply interruption circuit section (for example, see Japanese Patent Application Laid-Open Publication No. 2006-237189).
The semiconductor integrated circuit device proposed in the aforementioned publication includes a power control register configured to hold information that shows a power supply status of a function block, and has a power control circuit that controls the supply or interruption of power to a function block in accordance with information that is held in the power control register. For example, by providing the power control circuit with a timer function it is possible to “restore power minutes after power is interrupted”.
In an LSI which adopts this type of internal partial power supply interruption technology, in some cases a path that becomes an asynchronous data path according to an asynchronous clock exists between internal partial power supply interruption circuit sections or between a constant power supply circuit section and an internal partial power supply interruption circuit section. With an asynchronous data path that straddles a boundary surface of an internal partial power supply interruption circuit, a problem may arise with regard to the circuit scale or power consumption that does not occur with an ordinary asynchronous data path. Specifically, the following situation may arise.
Because a power control circuit that is an internal partial power supply interruption control circuit section also performs restoration control from a state in which power of an internal partial power supply interruption circuit section has been interrupted, the power control circuit is a circuit that is constantly supplied with power. Therefore, in a case in which the power of an internal partial power supply interruption circuit section is interrupted, a standby power of the overall circuit is an operating power of the internal partial power supply interruption control circuit section. Hence, with an LSI that is used for a device in which standby power is important, such as a portable device or a sensor network, it is important to lower the operating power of the internal partial power supply interruption control circuit section.
Further, in order to perform power interruption/restoration control, the internal partial power supply interruption control circuit section exchanges control values or data with a processor via a bus and a bus interface or via an interrupt circuit. In a case in which the bus interface and the interrupt circuit are internal partial power supply interruption circuits, it is necessary to insert an isolation cell on a data path to the internal partial power supply interruption control circuit section. The isolation cell is configured by an AND gate or an OR gate, and the data path is fixed to “0” or “1” to prevent propagation of an undefined output when the power is interrupted.
Accordingly, there has been the problem that, with respect to the internal partial power supply interruption control circuit section, unintended updating of data is performed at the control register by the fixed value of “0” or “1”. For example, a malfunction is caused by a control register that has been originally set to “1” being overwritten with “0” by propagation of a fixed value “0” when power is interrupted. When a countermeasure is implemented to prevent this kind of unintended updating of a control register, the circuit scale of the internal partial power supply interruption control circuit section increases.
Further, as described above, since the internal partial power supply interruption control circuit section is a circuit to which power is constantly supplied, it is desirable from the viewpoint of reducing power consumption that an operating frequency be as low as possible. In contrast, a high frequency is desirable for the bus interface and the interrupt circuit from the viewpoint of processing speed. Accordingly, a data path to a bus interface and an interrupt circuit and to an internal partial power supply interruption control circuit section is made an asynchronous data path, and a synchronizing circuit design is required.
One method that is well known as a synchronizing circuit that ensures an asynchronous data path is a method that provides multiple stages of flip-flops on a data receiving side (for example, see Atrenta, Inc. “Spyglass Clock-Reset Rules Reference Version 3.9.2” (pp. 98 to 114) January 2008 (hereafter, referred to as “Non-Patent Document 1”). However, according to the synchronizing circuit described in Non-Patent Document 1, there is the problem that the scale of the circuit on the receiving side increases. When this method is applied to a circuit for which it is desired to reduce an operating power such as an internal partial power supply interruption circuit section, there is the problem that since the circuit scale increases, a standby electric current increases.
Thus, conventionally, on an asynchronous data path from an internal partial power supply interruption circuit to an internal partial power supply interruption control circuit, there has been the problem that a control value can be rewritten by a fixed value of an isolation cell. Further, since the circuit scale of an internal partial power supply interruption control circuit increases when a synchronizing design is adopted for an asynchronous data path, there has been the problem that a standby electric current increases.